AI-infrastructure signals from the last 24 hours, ranked by significance.
The author argues the market undervalues AMD by viewing it as a GPU second source rather than a full-stack player, a narrative shift that drives multiple expansion.
The post uses Micron's own capacity figures to argue the DRAM shortage is a structural, time-inelastic supply bottleneck that persists into 2028-2029 rather than a normal cycle peak.
The author argues today's DRAM shortage is structural, not cyclical: HBM eats far more wafer capacity than standard DRAM, new fabs don't arrive until 2027 and get allocated to HBM first, and the three makers are deliberately withholding aggressive expansion. This locks in tight supply and pricing power for memory makers like Micron through 2028-2029.
NVIDIA's reported halving of Vera Rubin CPU-side DRAM sent Micron shares down, but the author argues a memory-demand collapse read is premature because lower per-system capacity could loosen supply and lift system count.
NVIDIA is reportedly lowering the SOCAMM standard build from 192GB to 96GB modules, cutting CPU-side DRAM per rack from ~54TB to ~28TB, which dragged Micron down. The author argues this is not necessarily a demand collapse: SOCAMM bit demand is the product of module capacity, modules per system, and systems shipped, so a lower per-system content can be offset if loosened supply lets more systems install. HBM4 capacity holds while bandwidth nearly triples, and Micron is preparing the HBM4 hot lane and SOCAMM2 for Vera Rubin.
Phone and PC memory capacity is the critical bottleneck for on-device model size, requiring LPDDR6 transition and 24GB configurations.
Micron is evaluating MicroLED optical interconnect technology alongside Samsung and SK hynix to solve memory fabric bandwidth and power constraints.
Micron, alongside Samsung and SK hynix, has invested in and is seriously evaluating MicroLED optical interconnect (Avicena's LightBundle) because its 'wide and slow' parallelization philosophy mirrors HBM's, and optics could free memory from package geometry constraints. The investment is framed as insurance on what comes after HBM rather than a near-term product plan.
Raises critical questions about China's ability to circumvent export controls on ASML's advanced lithography equipment, potentially undermining the efficacy of Western technological restrictions.
TSMC's next-generation CoPoS panel-level packaging roadmap is the channel through which glass enters advanced packaging, with a pilot line targeted for completion this year.
AI accelerator packages have outgrown organic substrates and the lithography reticle limit, forcing a shift to larger square panels (panel-level packaging) and glass materials. TSMC's CoPoS (Chip-on-Panel-on-Substrate) is the vehicle for this transition, with glass currently most solidly positioned on the temporary carrier side and a pilot line on schedule to finish within the year.
The post centers on TSMC's CoPoS roadmap as the successor to CoWoS, detailing the timeline, pilot site, and the unresolved questions of where glass fits and when mass production lands.
TSMC is developing CoPoS (Chip on Panel on Substrate) as the next step beyond CoWoS, using square panels instead of round wafers to fit ever-larger AI accelerator chips with less edge waste. The direction is clear but both glass's structural role and the mass-production timeline remain undecided, with the chairman warning there are no shortcuts.
TSMC's partnership with Avicena to optimize photodetector arrays on existing CIS processes gives it manufacturing advantage in optical interconnect scaling.
TSMC is positioning across optical interconnect technologies, partnering with Avicena (April 2025) to use its CMOS image sensor processes for photodetector arrays and investing through VentureTech Alliance. This is a foundry's hedge against silicon photonics CPO, leveraging an existing high-volume CIS ecosystem.
WSE-3 achieves materially higher inference decode speed than NVIDIA's current GPUs through on-chip SRAM, presenting competitive pressure in NVIDIA's inference market.
The author frames NVIDIA's GPU architecture as structurally advantaged over Cerebras's wafer-scale design: hardware support for multiple precisions plus the CUDA software ecosystem lets rapid software innovation convert directly into performance, while Cerebras's fixed FP16 hardware is 'forever chasing one generation behind.' Even where Cerebras wins on raw decode speed, NVIDIA retains workload portability and dominates training and frontier-scale serving.
Cloud AI's GPU-centered business model doesn't extend to edge devices, where hardware bottlenecks vary fundamentally by form factor.
NVIDIA is reportedly cutting the standard SOCAMM/DRAM configuration of Vera Rubin NVL72 to ship racks sooner amid LPDDR5X supply constraints, concentrating the expensive HBM4 lane on hot inference state.
NVIDIA's GPU-plus-HBM packages drive the CoWoS demand pushing packaging toward glass, and NVIDIA executives reportedly visited Nittobo to secure T-glass volume.
NVIDIA is cited as the first customer for TSMC's CoPoS mass production, with the Rubin Ultra generation expected to use a mix of CoWoS and CoPoS.
The post notes NVIDIA's NVLink has effectively monopolized the scale-up interconnect domain, which ALAB is now challenging via open standards.
Nvidia appears only as a section header claiming it seeks to control the entire memory hierarchy as an interface, with the supporting body truncated.
AMD's acquisition of software startup MEXT is presented as a strategic move to route around the DRAM bottleneck by letting flash behave like DRAM, signaling DRAM-light architecture intent.
The author frames AMD's purchase of MEXT as evidence that leading chip buyers have stopped waiting for memory prices to fall and are instead building 'detour' paths that use less DRAM. Buying a software prediction layer rather than a chip or memory part signals where the memory market is heading over the next few years.
AMD is named as the qualification customer for Absolics' glass core substrate at its Georgia fab, indicating AMD is an early adopter in the glass packaging supply chain.
Microsoft has entered the MicroLED optical interconnect field as part of broader datacenter bottleneck-solving strategy.