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Research history/TSM

TSM

Taiwan Semiconductor Manufacturing Co Ltd

High Conviction

Indispensable leading-edge foundry: Q1 2026 gross margin 66.25%, operating margin 58.1%, ROIC TTM 30.84%, forward P/E 21.86 / PEG 0.66. Near-monopoly on AI-compute manufacturing; -6.69% pullback today from a fresh 52w high set 2026-06-03.

Researched 11 days ago

Earnings Jul 15· After close· in 4 weeks

High Conviction
Conviction78
Upside22
Risk-adj0
Holdbelow $335.00

Indispensable leading-edge foundry: Q1 2026 gross margin 66.25%, operating margin 58.1%, ROIC TTM 30.84%, forward P/E 21.86 / PEG 0.66. Near-monopoly on AI-compute manufacturing; -6.69% pullback today from a fresh 52w high set 2026-06-03.

ScoresAnalyst DDAnalystSince lastRed flagsThesisConvictionQualityFinancialsValuationUpsideCycleCatalysts / RisksSizingRed-teamExpectationsFalsifiersSources

Recommendation

Hold

Quality holds but price is in the fair range — no action.

Recommendation

Hold

Conviction

78/100

high conviction

Upside

22/100

bull 30% · ~45% odds · +10% expected

Risk-adjusted upside

0/100

+0% after downside pressure

Thesis quality

8.7/10

Opportunity

4.6/10

Risk pressure

8.0/10

Valuation

Fair

AI fair value

$430.00

Fundamentals check

$427.46

12-24mo fair-value range

$350.00 / $430.00 / $510.00

width 37%

Buy below

$335.00

Trim above

$612.00

Implied expectations

achievable

29.1% implied revenue CAGR

Today's P/S implies ~29.1% revenue CAGR for five years versus 31.6% realized growth.

Analyst take (Substack DD)

  • damnangPartial

    Agree that TSMC leveraging its high-volume CIS process for Avicena photodetector arrays is a low-cost, strategically sound hedge across optical-interconnect paths and reinforces its packaging breadth. Push back on materiality and timing: MicroLED-based CPO is multi-year, unproven at scale (TrendForce sees the market only forming ~2028), with fiber-bundle packaging as a cited bottleneck. It is a credible medium/long-term optionality layer, not a near-term earnings driver, and does not by itself change the foundry thesis or verdict.

Since Last Research

Material changes

  • Price -6.69% on 2026-06-07 to 415.17 from near a fresh 52w high; distance-from-high widened from ~-1.5% to ~-8%.
  • New 52-week high 2440 set 2026-06-03 (up from 2375 on 2026-05-29).
  • Analyst strong-buy count eased 12 to 11 month-over-month (June); overall consensus still 0 sell.
  • New TIER_A Substack DD added on TSMC-Avicena optical/MicroLED interconnect positioning.

Unchanged thesis elements

  • Wide moat from leading-edge process dominance, CoWoS control and customer PDK lock-in.
  • Thesis scores unchanged: direct exposure 9, pricing power 9, defensibility 9; HIGH_CONVICTION maintained.
  • Net-cash balance sheet, 30.84% ROIC TTM and expanding margins intact.
  • Insider signal remains mixed/neutral.
  • Fair value ~$430/ADR and 5-10% sizing band unchanged.

Red flags

  • Taiwan geopolitical concentration is a binary structural tail risk on leading-edge capacity (itemized symmetrically vs peers).
  • Mixed insider signal: open-market sale of 200,000 shares by Chuang Tzu-Sou (2026-05-19) and a 150,000 derivative disposition (2026-05-22) partially offset several small director/officer purchases; net signal neutral.
  • Sharp -6.69% single-day decline (2026-06-07) from a fresh 52w high set 2026-06-03 signals elevated momentum/positioning risk.

AI-Infrastructure Thesis Fit

Foundry / advanced packagingNetworking / custom ASICs / switching siliconAI servers / hardware integrationOptical / CPO / silicon photonics
Direct exposure9/10
Pricing power9/10
Defensibility9/10

TSMC is the singular manufacturing bottleneck for AI hardware: NVIDIA Blackwell/Rubin, AMD MI-series, Google TPU, Amazon Trainium and Broadcom custom ASICs all depend on TSMC N3/N2 nodes and CoWoS packaging. Margin expansion to 66.25% gross / 58.1% operating reflects AI-node pricing power, with ROIC TTM rising across eight consecutive quarters to 30.84%. N2 ramp, Arizona fabs and emerging CPO/optical packaging (COUPE, Xintec, Avicena) add growth and optionality; rivals remain behind on yield and scale.

Conviction Assessment

Moat

Wide, widening moat: multi-year node lead, CoWoS capacity control, PDK lock-in; 66.25% gross margin proves pricing power.

Bottleneck fit

The single manufacturing bottleneck for AI compute; N3/N2 and CoWoS underpin all major accelerators.

Valuation

Forward P/E 21.86 / PEG 0.66 is reasonable for 30%+ ROIC and 30%+ growth; today's pullback improves entry.

Catalyst

N2 ramp and COUPE/CPO mass production starting H2 2026 are identifiable near-term catalysts.

Bull

  • Near-monopoly on leading-edge AI manufacturing with sustained pricing power and 66.25% gross margin
  • ROIC TTM rising eight straight quarters to 30.84% on a net-cash balance sheet
  • N2 ramp, CoWoS expansion and CPO/optical optionality extend the growth runway
  • Forward PEG 0.66 leaves valuation undemanding relative to growth

Bear

  • Taiwan geopolitical concentration is a binary structural tail risk
  • Heavy AI-capex/customer concentration exposes utilization to a demand-cycle digestion
  • Premium multiple (P/S 11.1) is vulnerable to compression, as the -6.69% drop today shows
  • Capital intensity of N2 and overseas fabs could pressure margins if utilization slips

Business Quality

Description

World's largest dedicated semiconductor foundry, manufacturing leading-edge logic chips (N3/N2) and advanced packaging (CoWoS) for the dominant AI-compute and mobile customers.

Value Chain

Critical component/infrastructure layer: turns chip designs into physical leading-edge silicon and packaged compute modules; the manufacturing bottleneck beneath every major AI accelerator.

Moat

wide

Multi-year process-node lead, CoWoS/advanced-packaging capacity control, and deep customer PDK lock-in; Samsung and Intel Foundry trail on yield and scale. 66.25% gross margin and 30.84% ROIC TTM evidence durable pricing power.

Pricing Power

high

Gross margin expanded from 53.2% (2024-06) to 66.25% (2026-03) on AI-node demand, demonstrating ability to raise leading-edge wafer pricing without losing share.

Customer Concentration

High exposure to a small set of AI/hyperscaler and mobile customers (NVIDIA, AMD, Apple, Google, Broadcom). Exact top-customer share not disclosed in packet.

Financial Health

MetricValue
Revenue growth YoY35.10%
Gross margin66.25% ↑
Operating margin58.10%
FCF margin30.70%
Cash position104000000000
Net debt / EBITDA-1
Share count change YoY0%
ROIC30.84%

Valuation

Forward P/E

21.86

Trailing P/E

23.66

PEG

0.66

EV/EBITDA

18.54

P/S

11.12

Sector: premiumHistory: in_line
PeerMetricValue
2303.TWgross marginUMC mature-node foundry, margins well below TSMC's 66.25%; no leading-edge or CoWoS exposure
INTCcontextIntel Foundry loss-making, nodes behind on yield/scale; TSMC premium justified by execution gap
2454.TWcontextMediaTek fabless customer, key TSMC volume driver in mobile/edge AI, not a margin peer

Upside Case

Bull fair value

$600.00

Probability

45%

Horizon

Long term

Sustained N2/CoWoS pricing power as AI compute demand compoundsOverseas fab footprint de-risks Taiwan concentrationCPO/optical packaging adds a new high-margin revenue layer

Cycle Position

YTD

—

1Y

17.52%

Vs sector

—

From 52w high

-8%

Valuation: in_lineAnalysts: neutralInsiders: neutral

Catalysts & Risks

Near-term catalysts

  • COUPE chip-on-organic (CPO) packaging mass production starting H2 2026 via subsidiary Xintec (per TIER_A X commentary)
  • Continued AI-driven leading-edge demand from hyperscaler capex (Google/Berkshire ~$80B AI buildout cited by TIER_A X)
  • Sustained gross-margin expansion as N3/N2 mix rises

Medium-term catalysts

  • N2 node ramp and Arizona fab capacity additions (geopolitical optionality)
  • AI optical / CPO market formation (Avicena CIS-process partnership, FOCI/MSScorps ecosystem)
  • CoWoS capacity expansion easing AI-accelerator supply constraints
RiskSeverityExplanation
Taiwan geopolitical concentrationhighLeading-edge capacity is concentrated in Taiwan; a blockade or conflict is a binary structural tail risk. Itemized symmetrically against AI-infrastructure peers.
Customer / end-market concentration on AI capexmediumHeavy reliance on a small set of AI/hyperscaler customers; an AI-capex slowdown or in-housing shift would pressure leading-edge utilization and pricing.
Valuation and cyclicalitymediumPremium multiple (PS 11.1, EV/EBITDA 18.5) leaves room for compression if the AI-capex cycle digests; a -6.69% single-day drop today shows momentum sensitivity.

Position Sizing

5%–10%

HIGH_CONVICTION with wide widening moat, net-cash balance sheet, 30.84% ROIC TTM, expanding margins and forward P/E 21.86 / PEG 0.66. Size toward 5% if Taiwan tolerance is limited or AI-hardware exposure is already heavy; toward 10% in AI-tilted portfolios with explicit Taiwan risk acceptance. Today's pullback offers a modestly better entry.

Sources

ClaimSourceURLRetrieved
Current price 415.17, -6.69% on the dayfinnhub:quote—retrieved 2026-06-07T22:38:42.870Z
Q1 2026 gross margin 66.25%, operating margin 58.1%, net margin 50.48%finnhub:basic-financials—as of 2026-03-31 · retrieved 2026-06-07T22:38:42.631Z
ROIC TTM 30.84%, ROE TTM 36.93%, FCF margin 30.7%finnhub:basic-financials—as of 2026-03-31 · retrieved 2026-06-07T22:38:42.631Z
Forward P/E 21.86, forward PEG 0.66, trailing P/E 23.66, EV/EBITDA 18.54, P/S 11.12finnhub:basic-financials—as of 2026-03-31 · retrieved 2026-06-07T22:38:42.631Z
52-week high 2440 set 2026-06-03; 52-week price return 17.52%finnhub:basic-financials—as of 2026-06-03 · retrieved 2026-06-07T22:38:42.631Z
Net cash position (net debt/total equity -0.34); current ratio 2.49finnhub:basic-financials—as of 2026-03-31 · retrieved 2026-06-07T22:38:42.631Z
Revenue/share YoY ~35.1% (Q1'26 vs Q1'25); FY ~31.6%finnhub:basic-financials—as of 2026-03-31 · retrieved 2026-06-07T22:38:42.631Z
Analyst recommendations June 2026: 11 strong buy, 29 buy, 2 hold, 0 sell (12 strong buy in May)finnhub:recommendations—as of 2026-06-01 · retrieved 2026-06-07T22:38:42.607Z
Insider activity: 200k-share sale (Chuang, 2026-05-19), 150k derivative disposition (2026-05-22), several small officer/director purchasesfinnhub:insider-transactions—as of 2026-05-22 · retrieved 2026-06-07T22:38:42.608Z
Industry: Semiconductors; listed Taiwan Stock Exchange (2330.TW)finnhub:profileLinkretrieved 2026-06-07T22:38:42.601Z
COUPE/CPO mass production via Xintec starting H2 2026x:@aleabitoredditLinkas of 2026-06-05 · retrieved 2026-06-07T22:38:42.450Z
Hyperscaler AI capex (Google/Berkshire ~$80B) supports foundry demandx:@aleabitoredditLinkas of 2026-06-01 · retrieved 2026-06-07T22:38:42.450Z
TSMC-Avicena CIS-process partnership for optical interconnect photodetector arrayssubstack:damnangLinkas of 2026-06-04 · retrieved 2026-06-07T22:38:42.451Z
Macro: 10Y 4.47%, Fed funds 3.62% (2026-06-04)fred:macro-snapshot—as of 2026-06-04 · retrieved 2026-06-07T22:18:20.706Z

Analyst DD (Substack)

  • 6Substack · damnang·NEUTRAL / EXECUTION·3 days agopost

    TSMC is developing CoPoS (Chip on Panel on Substrate) as the next step beyond CoWoS, using square panels instead of round wafers to fit ever-larger AI accelerator chips with less edge waste. The direction is clear but both glass's structural role and the mass-production timeline remain undecided, with the chairman warning there are no shortcuts.

    Evidence
    • First panel format is 310mm x 310mm, with a cited roadmap growing through 515mm x 510mm up to 750mm x 620mm
    • A round 12-inch wafer yields only four to seven large packages per sheet, which a square panel improves on
    • Pilot line laid down at TSMC subsidiary VisEra in 2026; press accounts cite small trial production in 2027 and mass production in 2028-2029
    • Chairman C.C. Wei stated mass production takes another two to three years with no shortcuts; some on the ground see 2029-2030
    • Mass-production site is the fourth phase of the AP7 campus in Chiayi, Taiwan, with NVIDIA cited as first customer
    • TSMC validated a 0.8-millimeter glass core substrate with Ibiden and Innolux under a program named 'glass substrate for CoWoS', while saying mass production is still far off
    Catalysts
    • VisEra pilot line in 2026
    • Trial production cited for 2027
    Risks
    • Whether glass enters as interposer or core substrate is unfixed, and which path reaches mass production first is open
    • Thin glass interposer (~400 micrometers) makes CTE management tricky and warpage worsens as the panel grows, repeatedly cited as the biggest barrier
    • Timeline weighted toward slipping, possibly to 2029-2030
    • Intel and Samsung are pushing competing panel packaging and glass approaches
  • 6Substack · damnang·NEUTRAL / EXECUTION·5 days agopost

    AI accelerator packages have outgrown organic substrates and the lithography reticle limit, forcing a shift to larger square panels (panel-level packaging) and glass materials. TSMC's CoPoS (Chip-on-Panel-on-Substrate) is the vehicle for this transition, with glass currently most solidly positioned on the temporary carrier side and a pilot line on schedule to finish within the year.

    Evidence
    • TSMC's current CoWoS binds an NVIDIA GPU and HBM into one package using a silicon interposer
    • Reticle limit is ~26 x 33mm (~858 sq mm); AI accelerators crossed it long ago and stitch multiple dies together
    • TSMC's package area roadmap moves from 5.5x the reticle to 9.5x then 14x; 9.5x is roughly 8,000 sq mm (~9cm per side)
    • Per Ming-Chi Kuo's June industry check, CoPoS uses a 310 x 310mm glass carrier, with a 510 x 515mm glass panel processed into a glass core substrate floated at the volume stage
    • TSMC is moving on schedule to finish the pilot line for next-generation panel packaging within the year
    Catalysts
    • Completion of the CoPoS pilot line within the year
    • Transition to panel-level packaging (PLP) raising area utilization above 75 percent
    Risks
    • Glass replacement of the silicon interposer classified by Taiwanese industry press as a long-term task
    • Core substrate adoption for CoPoS is closer to industry check and estimate than confirmation; what substrate early volume runs use remains open
    • Glass is brittle, making yield and customer qualification the central hurdle
  • 6Substack · damnang·BULLISH / EXECUTION·15 days agopost

    TSMC is positioning across optical interconnect technologies, partnering with Avicena (April 2025) to use its CMOS image sensor processes for photodetector arrays and investing through VentureTech Alliance. This is a foundry's hedge against silicon photonics CPO, leveraging an existing high-volume CIS ecosystem.

    Evidence
    • April 2025 collaboration to use TSMC CIS processes to optimize and mass-produce LightBundle photodetector arrays
    • VentureTech Alliance (TSMC's VC arm) joined Avicena's May 2025 $65M Series B
    • Silicon PD arrays are already mass-produced by the CIS industry at scale of hundreds of millions of pixels
    • Described as a foundry's hedge: not going all-in on silicon photonics CPO while keeping a foot on MicroLED
    Catalysts
    • PD array mass-production collaboration repurposing existing CIS portfolio
    • MicroLED-based CPO market projected by TrendForce to form in 2028, reaching $850M by 2030
    Risks
    • MicroLED interconnect commercialization path is multi-year and unproven at scale
    • Fiber bundle and packaging cited as the likely production bottleneck
    • Proprietary architecture with no standards ecosystem